VHDL: state machine (semaphore)

-- ~ --
-- www.asic-digital-design.com
-- ~ --
library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;
-- ~ --
entity fsm is
port (
  clk, rst : in std_logic;
  start    : in std_logic;

  red     : out std_logic;
  orange  : out std_logic;
  green   : out std_logic
);
end fsm;
-- ~ --
architecture arch_rtl of fsm is
  -- states
  type fsm_states is (
    st_red,
    st_red_orange,
    st_green,
    st_green_wait,
    st_orange,
    st_red_end
  );
  -- signals declaration
  signal reg_fsm, nxt_fsm   : fsm_states;
begin

  -- state machine
  dff_fsm: process(rst, clk)
  begin
    if (rst = '1') then
      reg_fsm <= st_red;
    elsif (clk'event and clk = '1') then
      reg_fsm <= nxt_fsm;
    end if;
  end process dff_fsm;

  cmb_fsm: process(reg_fsm, start)
  begin
    nxt_fsm <= reg_fsm;
    case reg_fsm is
      when st_red =>        if (start = '1') then
                              nxt_fsm <= st_red_orange;
                            end if;
      when st_red_orange =>   nxt_fsm <= st_green;
      when st_green =>        nxt_fsm <= st_green_wait;
      when st_green_wait =>   nxt_fsm <= st_orange;
      when st_orange =>       nxt_fsm <= st_red_end;
      when st_red_end =>    if (start = '0') then
                              nxt_fsm <= st_red;
                            end if;
    end case;
  end process cmb_fsm;
  
  cmb_fsm_out: process(reg_fsm)
  begin
    red    <= '0'; orange <= '0'; green  <= '0';
    case reg_fsm is
      when st_red =>          red    <= '1';
      when st_red_orange =>   red    <= '1'; orange <= '1';
      when st_green =>        green  <= '1';
      when st_green_wait =>   green  <= '1';
      when st_orange =>       orange <= '1';
      when st_red_end =>      red    <= '1';
    end case;
  end process cmb_fsm_out;

end arch_rtl;