Build your own FPGA design

Introduction

The aim of this chapter is to show you how simple can be to implement simple design to FPGA :) Our goal is to implement "Moving pixel on the 32x8 LEDs dot matrix"

The list of steps we will follow:

1. prepare the design architecture (block schematic)
2. write VHDL codes of design blocks
3. FPGA implementation
4. FPGA programming
5. Switch On & Debugging

VHDL: 32x8 LEDs with MAX7219 driver

VHDL: state machine (semaphore)

-- ~ --
-- www.asic-digital-design.com
-- ~ --
library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;
-- ~ --
entity fsm is
port (
  clk, rst : in std_logic;
  start    : in std_logic;

  red     : out std_logic;
  orange  : out std_logic;
  green   : out std_logic
);
end fsm;
-- ~ --
architecture arch_rtl of fsm is
  -- states
  type fsm_states is (
    st_red,
    st_red_orange,
    st_green,
    st_green_wait,
    st_orange,
    st_red_end
  );
  -- signals declaration
  signal reg_fsm, nxt_fsm   : fsm_states;
begin

  -- state machine
  dff_fsm: process(rst, clk)
  begin
    if (rst = '1') then
      reg_fsm <= st_red;
    elsif (clk'event and clk = '1') then
      reg_fsm <= nxt_fsm;
    end if;
  end process dff_fsm;

  cmb_fsm: process(reg_fsm, start)
  begin
    nxt_fsm <= reg_fsm;
    case reg_fsm is
      when st_red =>        if (start = '1') then
                              nxt_fsm <= st_red_orange;
                            end if;
      when st_red_orange =>   nxt_fsm <= st_green;
      when st_green =>        nxt_fsm <= st_green_wait;
      when st_green_wait =>   nxt_fsm <= st_orange;
      when st_orange =>       nxt_fsm <= st_red_end;
      when st_red_end =>    if (start = '0') then
                              nxt_fsm <= st_red;
                            end if;
    end case;
  end process cmb_fsm;
  
  cmb_fsm_out: process(reg_fsm)
  begin
    red    <= '0'; orange <= '0'; green  <= '0';
    case reg_fsm is
      when st_red =>          red    <= '1';
      when st_red_orange =>   red    <= '1'; orange <= '1';
      when st_green =>        green  <= '1';
      when st_green_wait =>   green  <= '1';
      when st_orange =>       orange <= '1';
      when st_red_end =>      red    <= '1';
    end case;
  end process cmb_fsm_out;

end arch_rtl;

VHDL: n-bit ripple counter

For description see: Asynchronnous binary counter (ripple counter)

-- ~ --
-- www.asic-digital-design.com
-- ~ --
library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;
-- ~ --
entity ripple_cnt is
generic (
  n : natural := 4
);
port (
  clk   : in std_logic;
  clear : in std_logic;

  b     : out std_logic_vector(n-1 downto 0)
);
end ripple_cnt;
-- ~ --
architecture arch_rtl of ripple_cnt is
  -- signals declaration
  signal clk_i, q_i   : std_logic_vector(n-1 downto 0);

begin
  -- clocks
  clk_i(0)            <= clk;
  clk_i(n-1 downto 1) <= q_i(n-2 downto 0);

  -- flip-flops
  gen_cnt: for i in 0 to n-1 generate
    dff: process(clear, clk_i)
    begin
      if (clear = '1') then
        q_i(i) <= '1';
      elsif (clk_i(i)'event and clk_i(i) = '1') then
        q_i(i) <= not q_i(i);
      end if;
    end process dff;
  end generate;
  
  -- output
  b <= not q_i;
  -- ~ --
end arch_rtl;